`include "defines.v"
// `timescale 1ns/1ps
module openmips_min_sopc_tb;
	reg clk;
	reg rst;
	
	openmips_min_sopc openmips_min_sopc0(
		.clk(clk),
		.rst(rst)
	);

	always #5 clk = ~clk;
	initial 
	begin
		clk = 0; rst = `RstEnable;
		#10 rst = `RstDisable;
		#1000 $stop;
	end
endmodule